While aluminum-based metallurgies have been the material of choice for forming metal interconnects for semiconductor devices in the past, concern has grown as to whether aluminum will meet the demands required as circuit density and speeds for semiconductor devices increase.
Other metals have therefore been investigated as possible replacements for aluminum-based metallurgies. One highly advantageous material now being considered as a potential replacement for aluminum metallurgies is copper, because of its low susceptibility to electromigration failure and its high conductivity, in comparison with aluminum.
However, copper suffers from a significant disadvantage: it readily diffuses into the surrounding dielectric material during subsequent processing steps and causes deleterious leakage between adjacent interconnect lines.
To inhibit the diffusion of copper, protective barrier layers are often used to isolate the copper interconnects from the surrounding dielectric material. For example, a conductive liner formed of a diffusion barrier material, such as tantalum, titanium, tungsten, and alloys or nitrides thereof, is provided along the sidewalls and bottom of the copper interconnect. Further, a dielectric diffusion barrier material, such as silicon nitride (Si3N4), is typically employed to cap the upper surface of the copper interconnect.
Silicon nitride capping layers formed by high density plasma chemical vapor deposition (HDP CVD) process exhibit superior electromigration protection characteristics by effectively stopping the movement of copper atoms along the interconnect surface in the cap layers. Further, such HDP CVD Si3N4 cap layers exhibit superior adhesion characteristics to the underlying copper metallization.
However, a silicon nitride film formed by a conventional HDP CVD process is characterized by a columnar growth pattern, as shown in FIG. 1. Specifically, the film grows only in an upward or vertical direction from the substrate surface, with little or no lateral growth. Because the underlying interconnect surface often contains one or more micro-steps (i.e., microscopic ledges or offsets that resemble steps of a stairway), either between the top surfaces of different device components, or at the copper grain boundary on the copper metallization, the columnar growth pattern of the HDP CVD film inevitably results in a seam (i.e., a gap or cavity) along each micro-step.
Formation of seams in the HDP CVD capping layer creates various problems, such as copper leakage, copper oxidation, resist poisoning, and blockage of via opening. For example, FIG. 2 shows a picture of an interconnect structure containing copper metallization covered by a conventional HDP CVD capping layer. After this structure was exposed to a sulfuric/peroxide solution (containing sulfuric acid and hydroperoxide), severe attack of the copper metallization line through seams in the HDP CVD capping layer was observed.
U.S. Patent Application Publication No. 2003/0134499 describes a bilayer HDP CVD/PE CVD cap, which comprises a first cap layer formed by a conventional HDP CVD process, and a second cap layer formed by a plasma-enhanced chemical vapor deposition (PE CVD) process. The second cap layer formed by the PE CVD process provides seamless coverage over the underlying structure and therefore mitigates the problems associated with the presence of seams in the first HDP CVD cap layer. Such a bilayer cap structure advantageously exhibits both superior electromigration protection and adhesion characteristics of a HDP CVD film, and the superior coverage characteristic of a PE CVD film.
However, in the bilayer cap structure described by U.S. Patent Application Publication No. 2003/0134499, a small amount of copper can still leak through the seams in the first HDP CVD cap layer to form copper dendrites between the first and the second cap layers, and fluorine contained in the inter-layer dielectric material formed of fluorinated silica glass (FSG) may also diffuse through such seams, as shown in FIG. 3.
Further, a low level of resist poisoning still exists in such a bilayer cap structure, because the PE CVD cap layer has a low reactive ion etching (RIE) selectivity over the inter-layer dielectric (ILD) oxide. Consequently, a portion (or a large portion) of the PE CVD cap layer may be deleteriously removed by via RIE, which leads to exposure (or partially exposing) of the seams of the underlying HDP film to subsequent processing steps.
FIG. 4 shows an interconnect structure that contains a first ILD layer 12 having a copper conductor 14 and a tantalum liner 16 embedded therein. A bilayer cap structure as described by U.S. Patent Application Publication No. 2003/0134499 is provided to cap the upper surface of the copper conductor 14. Such bilayer cap structure comprises a first HDP CVD cap layer 22 and a second, seamless PE CVD cap layer 24. A second ILD layer 26 is provided over the PE CVD cap layer 24, for forming additional interconnect structures therein. Because the PE CVD layer 24 has a low RIE selectivity over the ILD layer 26, when a RIE process is carried out to form a via 25 through the ILD layer 26, the underlying PE CVD layer 24 may be partially removed, or even completely punched through, exposing the seams in the underlying HDP CVD cap layer 22.
Moreover, the HDP CVD and the PE CVD processes required for fabricating the bilayer cap structure described by U.S. Patent Application Publication No. 2003/0134499 must be carried out in at least two different reactors, one for HDP CVD and the other for PE CVD, and additional wafer handling and transporting equipment is also needed for moving the wafer from one reactor to the other. Therefore, fabrication of this prior art bilayer cap structure involves complex processing steps with significantly increased processing time and manufacturing costs.
There is a continuing need for providing improved cap structures for semiconductor devices containing copper interconnects or other metal interconnects at lower costs.